A high performance ECC hardware implementation with instruction-level parallelism over GF(2163)

In this work we propose a high performance elliptic curve cryptographic processor over GF(2) for the applications that require high performance. It has three finite field (FF) RISC cores and a main controller to achieve instruction-level parallelism (ILP) for elliptic curve point multiplication. Customized instructions are proposed to decrease clock cycles. The interconnection among three FF cores and the main controller is obtained based on the analysis of both data dependency and critical path. The proposed design can reach 185 MHz with 20,807 slices when implemented on Xilinx XC4VLX80 FPGA device and 263 MHz with 217,904 gates when synthesized with TSMC .18 lm CMOS technology. 2010 Elsevier B.V. All rights reserved.